It is known that information processing systems with shared memory generally include a large number of processors, which are grouped in nodes associated with one another by links, in a variable number of nodes up to the maximum configuration. Each node includes a series of processors and one or more local memories, which are parts of a general memory. In a conventional configuration, the processors and the local memory or memories are all connected directly to a common linking bus of the parallel link type. This solution has the advantage of very direct access for each processor to each local memory, but it has the disadvantage of making all the interrogation and information transfer messages travel over the same linking bus, in such a way that the maximum rate of messages on the linking bus is very rapidly reached, and a problem of access to the linking bus then arises, since the messages that cannot be transmitted are made to wait until the linking bus is available. Moreover, when the number of processes is increased, the number of messages is also increased very greatly, on the one hand because of the interrogation and information transfer messages that are made necessary by the existence of the two processors, but also because of additional coherence messages that are required when a plurality of processors work on the same information and must modify the information while the information is simultaneously requested by other processors.
Conventionally, an attempt has been made to handle the increase in the message rate by improving the performance of the memory blocks, in particular increasing their access speed, and by improving the performance of the buses, that is, increasing the message transmission rate on the buses. Such improvements can generally be obtained only by using expensive technologies, which greatly increase the cost of the information processing system.
One object of the invention is to propose a processor node with an original structure that improves the message rates regardless of the technology used to make the memory blocks or linking buses.
According to the invention, a processor node is proposed, including at least one local bus that assures a parallel link between the processors, a local memory and a shared cache, and one network bus that assures a parallel link between the local memory, the shared cache, and one input/output device.
Thus the local bus is used only for transmitting messages that are directly useful to the processors, while the network bus is used for transmission of messages of links with the other nodes, in such a way that the number of messages circulating on each bus is minimized. While minimizing the message rate, it will be noted that this arrangement nevertheless enables simultaneous access to the local memory and to the shared cache, either by the local bus or by the network bus.